Minimum qualifications:Bachelor's degree or equivalent practical experience.8 years of experience in software development, with data structures/algorithms.

7 years of experience building and developing large-scale infrastructure, distributed systems, or networks, or with compute technologies, storage, or hardware architecture.5 years of experience with design and architecture, and testing/launching software products.Preferred qualifications:Experience working with hardware and software teams developing complex SoCs.

Experience in SOC performance model development and performance analysis.Experience in correlating modeled performance with RTL/Emulation/Silicon.Domain knowledge in CPU micro-architecture and SoC level architecture.

About the job Google Cloud's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google Cloud's needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve.

You will anticipate our customer needs and be empowered to act like an owner, take action and innovate. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward.As a Staff Software Engineer for SoC Performance Analysis, you will work closely with internal systems teams and SoC architecture teams to develop a comprehensive SoC that will drive SoC performance analysis.

You will analyze workloads and define performance improvements at the SoC level. You will develop a detailed understanding of the SoC micro-architecture, and identify the important performance metrics, benchmarks, measuring tools, and available optimization knobs. You will define the methods and technologies to model SoC performance at different accuracy levels, supporting architectural explorations, and decision making.

You will then correlate performance projections with measured post silicon data.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible.

We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.The US base salary range for this full-time position is $185,000-$283,000 + bonus + equity + benefits.

Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities Collaborate with System, SoC, and IP architects to understand model requirements. Analyze workloads and drive architecture analysis and evaluation of SoC design features.Perform correlation of I/O performance model with post-silicon measurements.

Communicate analysis results in both qualitative and quantitative fashion.Develop and maintain an architectural model of a high performance I/O Subsystem